P. V. Testa, Lazlo Szilagyi, Zoltan Tibensky, C. Carta, F. Ellinger
{"title":"A Compact Vector-Sum Phase Shifter for 5G Applications in 22 nm FD-SOI CMOS","authors":"P. V. Testa, Lazlo Szilagyi, Zoltan Tibensky, C. Carta, F. Ellinger","doi":"10.1109/RFIT49453.2020.9226241","DOIUrl":null,"url":null,"abstract":"This paper presents a vector-sum phase shifter for 5G applications at 28 GHz, implemented in a 22 nm FD-SOI CMOS technology. The component is formed by four VGAs which control the amplitude of quadrature and out-of-phase vectors generated on-chip with compact passive structures. A continuous 0°-360° phase control has been demonstrated with an average insertion loss of 9.5 dB at 28 GHz and a minimum RMS error of 0.4 dB and 4° when the power consumption PDC is 11.5 mW. The presented solution achieves the smallest active area while showing comparable performance for the other features against the state of the art.","PeriodicalId":283714,"journal":{"name":"2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT49453.2020.9226241","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
This paper presents a vector-sum phase shifter for 5G applications at 28 GHz, implemented in a 22 nm FD-SOI CMOS technology. The component is formed by four VGAs which control the amplitude of quadrature and out-of-phase vectors generated on-chip with compact passive structures. A continuous 0°-360° phase control has been demonstrated with an average insertion loss of 9.5 dB at 28 GHz and a minimum RMS error of 0.4 dB and 4° when the power consumption PDC is 11.5 mW. The presented solution achieves the smallest active area while showing comparable performance for the other features against the state of the art.