Highly parallel computations of creep deformation in flip-chip interconnections

Abstract

In order to enable the computation of creep deformation in a large number of interconnections in simulations of thermal cycling or assembly processes of flip chip devices, a submodeling approach was developed to distribute the stress and creep evaluation to independent solvers for individual (or small number of) interconnections and thus allow a high level of parallelization of the solving effort. The approach uses a first, coarser model of the complete assembly to compute the general system response to thermal and mechanical loads. Displacements calculated in this first model are fed into a large number of much more detailed models of the individual interconnections, in order to obtain local creep strains. The coarser model is iteratively updated using local creep values from the interconnection models to determine the complete time evolution of the system in the presence of interconnection creep deformation. The validity of the complete parallelized procedure is verified on simplified cases.