Analysis of electrical performance of a-SiGe:H Thin Film Transistors by numerical simulations

Abstract

This paper presents the study using 2D numerical simulations of main electrical parameters of different architectures of a-SiGe:H Thin Film Transistors (TFTs) such as subthreshold slope (S. S.), threshold voltage (Vth), ION/IOFF ratio, effective mobility (ueff) and cut-off frequency (fT). Was selected the architecture with the best electrical performance, which is the Staggered Bottom Gate, and then it was planarized the gate electrode by applying a lift-off process, as an optimization technique, in order to remove steps between drain/source electrodes and the active layer. Also, was made an analysis of the effect of gate oxide thickness on electrical performance, where, according to extracted results, the optimal thickness is 10 nm of SiO2 as gate oxide.