An inverter-based 6-bit pipelined ADC with low power consumption

I. Piatak, D. Morozov, J. Hauer
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引用次数: 4

Abstract

A 6-bit pipelined analog-to-digital converter (ADC) with low power consumption has been designed. Inverter-based comparators have been used. To provide 6 bits output code 2 stages of pipeline with resolution of 3 bits have been used. In each stage digital-to-analog converter (DAC) and amplifier were implemented without operational amplifiers (Op-amps). Cascode current mirrors with weighted currents have been used to enhance sampling rate. Thus, the results of computer simulation show that ADC achieves 200 Ms/s sampling rate and 1.87 mW power consumption (at ±0,9 V supply voltage). Reported DNL and INL are 0.67 LSB and 1.05 LSB respectively, SNDR and SFDR are 29.7 dB and 33.5 dB respectively, ENOB is 4.64 bit. Inverter-based comparators with reduced influence of manufacturing process and temperature variations were designed. Test chip for 2 bit stage of pipelined ADC was implemented using 180 nm mixed-mode CMOS UMC technology. The stage occupies 0.0026 mm2. Sampling rate is 500 Ms/s, power consumption is approximately. 970 uW.
基于反相器的6位流水线ADC,功耗低
设计了一种低功耗的6位流水线模数转换器(ADC)。已经使用了基于逆变器的比较器。为了提供6位的输出代码,使用了2级3位分辨率的管道。在每级数模转换器(DAC)和放大器的实现中都没有运算放大器(Op-amps)。采用带加权电流的级联电流镜提高了采样率。因此,计算机仿真结果表明,在±0.9 V电源电压下,ADC的采样率为200ms /s,功耗为1.87 mW。报道的DNL和INL分别为0.67 LSB和1.05 LSB, SNDR和SFDR分别为29.7 dB和33.5 dB, ENOB为4.64 bit。设计了基于逆变器的比较器,减小了制造工艺和温度变化的影响。采用180nm混合模式CMOS UMC技术实现了流水线ADC 2位级测试芯片。舞台占地0.0026 mm2。采样率为500ms /s,功耗约为。970年华盛顿大学。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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