A novel method to analyze and design a NWL scheme DRAM

Abstract

One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.