Performance comparison of GS-DG-FinFET with impact of high-K in various device Engineering

A. Pattnaik, S. K. Mohapatra
{"title":"Performance comparison of GS-DG-FinFET with impact of high-K in various device Engineering","authors":"A. Pattnaik, S. K. Mohapatra","doi":"10.1109/AESPC44649.2018.9033207","DOIUrl":null,"url":null,"abstract":"In this paper, the conventional structure of Double Gate (DG) FinFET has been modified using the booster techniques. The techniques considered for the simulations are Gate Stack (GS) and Spacer Engineering. With this we intended to provide a comparative study to suggest the possibility for better performance and to down scale the Short Channel Effects (SCEs). Both the DG-FinFET and GS-DG-FinFET with Spacers configuration are equated for Sub-threshold Slope (SS), the Threshold Voltage (VTH) roll-off, Drain Induced Barrier Lowering (DIBL), the Switching current ratio (ION/IOFF ratio) and electrostatic potential. The results are discussed by two ways of analysis a) by work function variation with Channel Length (Lg) constant b) by Lg variation with work function constant The Simulation is carried out considering 45 nm node parameters according ITRS road map. The Transconductance (gm) and Transconductance Generation Factor (TGF) are estimated.","PeriodicalId":222759,"journal":{"name":"2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)","volume":"20 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AESPC44649.2018.9033207","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
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Abstract

In this paper, the conventional structure of Double Gate (DG) FinFET has been modified using the booster techniques. The techniques considered for the simulations are Gate Stack (GS) and Spacer Engineering. With this we intended to provide a comparative study to suggest the possibility for better performance and to down scale the Short Channel Effects (SCEs). Both the DG-FinFET and GS-DG-FinFET with Spacers configuration are equated for Sub-threshold Slope (SS), the Threshold Voltage (VTH) roll-off, Drain Induced Barrier Lowering (DIBL), the Switching current ratio (ION/IOFF ratio) and electrostatic potential. The results are discussed by two ways of analysis a) by work function variation with Channel Length (Lg) constant b) by Lg variation with work function constant The Simulation is carried out considering 45 nm node parameters according ITRS road map. The Transconductance (gm) and Transconductance Generation Factor (TGF) are estimated.
高k影响下GS-DG-FinFET在各种器件工程中的性能比较
本文采用升压技术对双栅FinFET的传统结构进行了改进。仿真中考虑的技术有栅极叠加(GS)和间隔器工程。因此,我们打算提供一项比较研究,以建议更好的性能和缩小短通道效应(sce)的可能性。具有间隔配置的DG-FinFET和GS-DG-FinFET的亚阈值斜率(SS)、阈值电压(VTH)滚降、漏极感应势垒降低(DIBL)、开关电流比(ION/IOFF比)和静电电位均相等。通过功函数随通道长度(Lg)常数的变化和功函数随通道长度(Lg)常数的变化两种分析方法对结果进行了讨论,并根据ITRS路线图考虑了45 nm节点参数。估计了跨导(gm)和跨导产生因子(TGF)。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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