Performance comparison of GS-DG-FinFET with impact of high-K in various device Engineering

Abstract

In this paper, the conventional structure of Double Gate (DG) FinFET has been modified using the booster techniques. The techniques considered for the simulations are Gate Stack (GS) and Spacer Engineering. With this we intended to provide a comparative study to suggest the possibility for better performance and to down scale the Short Channel Effects (SCEs). Both the DG-FinFET and GS-DG-FinFET with Spacers configuration are equated for Sub-threshold Slope (SS), the Threshold Voltage (VTH) roll-off, Drain Induced Barrier Lowering (DIBL), the Switching current ratio (ION/IOFF ratio) and electrostatic potential. The results are discussed by two ways of analysis a) by work function variation with Channel Length (Lg) constant b) by Lg variation with work function constant The Simulation is carried out considering 45 nm node parameters according ITRS road map. The Transconductance (gm) and Transconductance Generation Factor (TGF) are estimated.