Via-Last TSV (From Top) Fabrication on a LNA SOI Wafer for 3D Heterogeneous Chiplet Integration

Abstract

This paper demonstrates the 3D heterogenous integration of integrated circuit chips through a vertical stack-up (of SiPs) approach to achieve significant reduction in form factor with improved performance. In this paper, the process integration of high aspect ratio via-last TSV in a LNA SOI wafer will be described. The final aim of this work is to allow a 3D integration for RF front ends as schematically shown in Fig. 1. The front side metallization on the LNA device wafer includes one layer of Cu BEOL while the backside of the wafer consists of one Cu re-distribution layer (RDL) interconnect layer. The RF testing will be performed to verify the TSV and interconnections on LNA SOI wafer. Fig. 1 shows the schematic of test vehicle with filter chip assembled on LNA wafer with TSV for demonstration purpose.