The design of multiplierless digital data transmission filters with powers-of-two coefficients

Abstract

An efficient search technique is presented for the design of FIR (finite impulse response) digital transmit and receive matched filters whose coefficients are represented by sums and/or differences of powers-of-two. These filters are ideally suited for custom VLSI implementation since power-of-two multipliers are obtained for free in a dedicated hardware implementation. Thus only a few adders or subtracters are required for each tap of the filter, and therefore fairly high-order filters can be implemented on a single VLSI chip. Due to their very simple structure these multiplierless filters could potentially operate at very high sampling rates to accommodate baud rates in the microwave digital radio range.<>