Modeling and analysis of read (RD) disturb in 1T-1STT MTJ memory bits

68th Device Research Conference Pub Date : 2010-06-21 DOI:10.1109/DRC.2010.5551946

A. Raychowdhury, D. Somasekhar, T. Karnik, V. De

引用次数: 9

Abstract

The paper presents a RD disturb model study of STT-MTJ memory bits. It shows that high-current short-pulsed RD may cause failure under hammer conditions. Analytical models for such have been developed and validated against numerical simulations.

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1T-1STT MTJ存储位读干扰建模与分析

本文研究了STT-MTJ存储位的RD干扰模型。结果表明，在锤击条件下，大电流短脉冲RD可能导致失效。这种分析模型已经开发出来，并通过数值模拟进行了验证。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

68th Device Research Conference

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