A high speed fully differential dynamic comparator for use in pipelined A/D converters

Abstract

This paper proposes the design of dynamic comparator for high speed Analog to Digital converters (ADCs). It features larger input swing, less sensitivity to common mode voltage and simple relationship between input and reference, and has low power dissipation. It is implemented in 0.18μm CMOS Technology. The simulation results are done in Cadence environment.