Sub 0.1 /spl mu/m nMOSFETs fabricated using experimental design techniques to optimise performance and minimise process sensitivity

Abstract

Bulk nMOS transistors with nominal poly length of 0.12 /spl mu/m and minimum effective channel length below 0.1 /spl mu/m were fabricated. Arsenic S/D shallow extensions and optimised channel doping by Indium were used to suppress the short channel effect (SCE) as well as the reverse-SCE. E-beam lithography was used for poly level definition and an advanced Co/Ti salicidation scheme was applied to reduce the sheet resistance to below 4 /spl Omega//square for poly widths down to 0.08 /spl mu/m. Design of Experiments (DOE) was used in defining the lot splits to study the influence of technological parameters on the device performance and its sensitivity to fluctuations in process parameters.