A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interface

Abstract

A low-power depth-estimation processor is proposed for mobile UI applications. We adopt hardware-friendly shift-only computations for exponentiation and multiplication in stereo algorithm to reduce power consumption down to 4.7mW with negligible accuracy loss. Also, the 7-stage shifter-register-based pipeline architecture with applying pipeline reordering optimization is deployed for reducing power and area. Utilization of the proposed pipeline architecture is 94% at 166MHz. The proposed algorithm and hardware co-optimization reduces required number of operations and external memory accesses by 85.5%, resulting in 75.6% lower energy consumption. The 1.47mm2 chip is fabricated with 65nm CMOS process and the resulting depth map is successfully used for hand segmentation.