The evolutionary design and synthesis of non-linear digital VLSI systems

Abstract

This paper describes a multi-objective evolutionary algorithm (EA) system for the synthesis of efficient non-linear VLSI circuit modules. The EA takes the specification for a non-linear block, and converts it into a technology independent netlist, specified in the Verilog hardware description language. The hardware designs are based upon highlevel components such as adders and multipliers. The circuit designs that are produced are near-optimal with respect to silicon area and longest-path delay. The performance of the EA is enhanced through the use of local searches. These searches are embedded within the genetic operators, and enable the rapid evaluation of large numbers of designs. The use of searches increases the power of the EA system, without forfeiting the benefits of using a population of solutions. The system is demonstrated with several test problems. Results are presented for the discovery of correct designs, and also regarding the quality of the evolved designs. The most complex designs have areas as large as 200,000/spl mu/m/sup 2/ in a 0.18/spl mu/m technology.