An analytical investigation of the effect of varied buffer layer designs on the turn-off speed for 4H-SiC IGBTs

Abstract

We propose a criterion to quantify the relationship between buffer layer parameters at a given total charge and turn-off speed for 4H-SiC IGBTs. Three phases of voltage ramp are analytically discussed during the inductive load turn-off by solving each corresponding continuity equation. Extra emphasis will be placed on Phase II - a transition phase in between the initial voltage ramp and punch-through.