Priority algorithm based VLSI testing technique for BIST

Abstract

The paper presents a low test time BIST based on Priority Algorithm (PA) is applied for the 32-bit Carry Look-Ahead Adder. This method assigns priority to the test patterns based on faulty coverage and independent faulty detecting test patterns. Experiment conducted on Cadences' RTL Compiler Tool and Cadences' Encounter Tool demonstrate that proposed scheme gives better performance with large reduction in test time and power dissipation during testing.