Automatic generation of test instructions for path delay faults based-on stuck-at fault in processor cores using assignment decision diagram

Abstract

This paper proposes a satisfiability-based automatic test instruction program generation to test the path delay faults using stuck-at fault in processor cores. Pre-computed test vectors are applied using the test instructions during normal processor execution. The proposed framework uses the assignment decision diagram (ADD) which represents the structural description of the register transfer level (RTL) circuit to extract the paths. ADD representation and instruction set architecture (ISA) information eliminates the paths that are untestable by the instructions during path extraction. The satisfiability (SAT)-solver is used to generate the sequence from conjunctive normal form (CNF) to find the justification/propagation paths. Test sequence is mapped to ISA to generate the test instruction program. A parwan processor module is used to validate our approach.