Triple poly II DRAM memory cell

Abstract

USING CONVENTIONAL PROCESSING techniques, a DRAM cell utilizing almost the entire cell area for the storage capacitor, has been developed. Thus, even with 300adielectric material, the storage capacitance has been found to provide improved results over prcviously reported 256K DRAM cell^"^'^. And without using s i l i ~ i d e s ~ ’ ~ ’ ~ double metal process2 or multiple row decoders4, upgraded performance has been possible. The layout of the cell is shown in Figure 1. Buried diffused bit lines are formed by an additional masking step that enables the bit lines to be implanted and oxidized prior to the deposition of Poly 1 and normal source/ drain implant. Poly 1 word lines form access transistors at areas where Poly 1 and active areas overlap with no bit line implant. In this manner Poly 1 word lines are able to cross buried bit lines without forming transistors. Poly 1 also forms transistors for the peripheral circuitry. Storage capacitor plates are formed by Poly 2 and Poly 3. The Poly 2 plate is connected to the sourcc of the access transistor by means of a buried contact. Since the Poly 2 capacitor plates lie on top of the word lines, bit lines, and access transistors, they can occupy the entire cell area. The only limitation is the physical spacing between adjacent capacitors. The common terminal for all storage capacitors is a sheet of Poly 3 covering the entire cell area. Metal lines are used to connect Poly 1 word lines outside the memory cell areas and only at desired intervals.