A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI:10.1109/MIXDES.2006.1706659

H. Lin, H. Lin, R. Chang, S.-W. Chen, Chih-Yuan Liao, C.-H. Wu

引用次数: 14

Abstract

A high-speed highly pipelined dual-input FFT/IFFT architecture efficiently sharing hardware is proposed for MIMO WLAN communication systems. It reduces the hardware complexity to enhance the throughput of the FFT/IFFT processor to be applied to IEEE 802.11n WLAN system or beyond. The area and the power consumption of the proposed design is 0.66mm2 and 97mW at 200MHz operation frequency with dual input/output 64-point FFT/IFFT sequences using TSMC 0.18mum 1P6M technology at supply voltage of 1.8V

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双Ofdm处理器的高速高流水线2n点FFT架构

针对MIMO无线局域网通信系统，提出了一种高速、高流水线的双输入FFT/IFFT架构，可以有效地共享硬件。它降低了硬件复杂度，提高了FFT/IFFT处理器的吞吐量，适用于IEEE 802.11n或更高的WLAN系统。在200MHz工作频率下，采用台积电0.18mum 1P6M技术的双输入/输出64点FFT/IFFT序列，电源电压为1.8V，设计的面积和功耗为0.66mm2和97mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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