A Memristor-CMOS Braun Multiplier Array for Arithmetic Pipelining

Abstract

A multiplier is a core building block in most digital signal and image processing systems and increasingly so in neural processing units. The latter must parallelize very large scale multiply-and-accumulate operations in deep learning with reconfigurable weights to be multiplied with varying input. In light of this, we propose a memristor-CMOS hybrid multiplier which uses a Braun structure to enable segmentation of the multiplier array to process various multiplication operations simultaneously with reconfigurable bit-widths by varying a control signal, all on the same multiplier. This enables an increase in computational throughput. Memristors are used as basic logic elements and improve area utilization by fabricating them in the back end of the line before the pad level. The CMOS chip is fabricated in the SK Hynix 180-nm process with TiO2 memristors separately deposited on top. A performance evaluation is undertaken under a 4-point Fast Fourier Transform, demonstrating a decrease in area by 17% and power consumption by 35%-49% with a 100MHz system clock when compared to similarly behaving CMOS multipliers.