Performance exploration and optimization of SDRAM-controller architecture on SDRAM access

Abstract

The access operation between CPU and off-chip memory, such as SDRAM, is very frequent in embedded system. This being the case, we try to take full advantage of SDRAM by developing a novel SDRAM-controller architecture. The architecture is based on the SDRAM characteristics with full instruction flow analysis. Three techniques are employed for auto adaptive prefetch instruction, overlapping read latency, locality of reference and reduction of row miss mainly aroused by accessing stack data. The results using benchmark programs show that developed architecture reduce the memory latency by 71% on average