Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion

Abstract

A current-steering ternary DAC is proposed to reduce the power consumption and size while retaining better resolution than conventional binary DACs. By applying the method proposed in this paper, a 4-trit ternary DAC is designed. It operates at 100MHz sampling rate and 1.8V supply voltage, and is implemented in 180nm CMOS technology. Compared to 6-bit binary DAC [5], it reduces power consumption by 31.69% to 30.64 %, and reduces area by 75.48 %.