{"title":"GaAs multichip module for a parallel processing system","authors":"T. Miyagi, K. Itoh, S. Kimijima, T. Sudo","doi":"10.1109/ECTC.1990.122246","DOIUrl":null,"url":null,"abstract":"A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3*4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Omega to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. the total thermal resistance from the chip to the ambient medium was approximately 3 degrees C/W. A 3-Gb/s data transfer rate (32 b*100 MHz) can be realized by four stacked modules of 48 GaAs BLs.<<ETX>>","PeriodicalId":102875,"journal":{"name":"40th Conference Proceedings on Electronic Components and Technology","volume":"129 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"40th Conference Proceedings on Electronic Components and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.1990.122246","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A high-speed data transfer network for a parallel processing system has been developed on the basis of multichip packaging technology. The high-speed data transfer network connecting multiple processor units (PUs) has been achieved in a module using 8 bit-slice GaAs bus logic (BL) LSIs operating at 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3*4 matrix. Each GaAs chip is sealed in a chip carrier with bumps. The chip carrier is flip-chip bonded to the copper/polyimide thin-film multilayer substrate. The characteristic impedance of the signal lines on the module is controlled to 75 Omega to be compatible with the GaAs original interface level. The thin-film termination resistors are made of Ni/Cr in the substrate to prevent reflections. A total power dissipation of 90 W of the module was efficiently radiated by a newly developed heat-pipe cooling module at 2-m/s air flow velocity with low acoustical noise. the total thermal resistance from the chip to the ambient medium was approximately 3 degrees C/W. A 3-Gb/s data transfer rate (32 b*100 MHz) can be realized by four stacked modules of 48 GaAs BLs.<>