Implementation of Low-Density Parity Check on Field Programmable Gate Array DE1-SoC

Abstract

Recently, telecommunications technology is growing rapidly, one of the devices that can support this development is a FPGA (Field Programmable Gate Array) which is an IC (Integrated Circuit) component and can be developed using programming. In this study, the authors use the DEl-SoC as an information bit transceiver board with LDPC (Low-Density Parity Check) coding technique because it can minimize errors approaching the Shannon limit with low BER (Bit Error Ratio). The information data that will be entered into the system is a binary bit which will be processed using a Linear Block Code encoder method, then the data is sent from the first FPGA DEl-SoC board as a transmitter to the second FPGA DEl-SoC board as a receiver. After that, the information data received at the second FPGA DEl-SoC as a receiver will be processed using a decoder so that it can be converted into binary bits of information data that are sent from the transmitter. This study successfully implemented the LDPC code on the DEl-SoC FPGA which was carried out through the Binary Symmetric Channel by utilizing UART (Universal Asynchronous Receiver-Transmitter) serial communication, where information is sent using 4 bits of binary as message input and 8 bits as the output codeword (1/2 code rate). Then in UART serial communication, the error percentage obtained is 0% because the data sent is the same as the data received.