Formal Method for the Rapid Verification of SystemC Embedded Components

Abstract

The SystemC language offers a mature technology to model complex embedded systems made up software and hardware parts, is became the soft hardware description language for the largest designers of embedded systems. In the final stages of systems construction, the designers must check and re-verify their reliability. The formal verification one of the research’s line of embedded designs checking, their methods based on the mathematical proves that know some limitations at the level of the big systems by cause of their exhaustive tricks. Those limitations affect directly the verification’s speed and cost. Our approach proposed is the deduction’s method to improve the quickness of SystemC designs’ verification, is stand on extracting the executions of equivalence, "paths of equivalence", through which we can deduct and prove the satisfaction of the systems specification. Previously, we are illustrated its functionality on the simple synchronous FIFO component. In this paper, we implement the deductions method to evaluate their performance on some test-benches with four processes and using binary coding to best manipulate the optimization part.