3-5 GHz CMOS Power Amplifier in 130nm CMOS for UWB Applications

N. G. El-Feky, Dina M. Ellaithy, M. Fedawy
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Abstract

A broadband CMOS power amplifier (PA) working in frequency range starting at 3 GHz to 5 GHz in 130 nm CMOS process for ultra-wideband (UWB) implementations is accomplished in this paper. A cascode scheme (common source transistor followed by common gate transistor) is employed in the design of the achieved power amplifier. To boost the power gain, two stages cascode amplifier with a common source (CS) scheme as the third stage are used covering the operating band. This PA attains a power gain of about 18.86 dB and reaches an excellent flatness of about ±0.3. The output P1dB is about −3 dBm. A broad range of impedance matching at input and output is accomplished. The input return loss (S11), the output return loss (S22), and the reverse isolation (S12) equal about <-5 dB, <−3 dB, and <-100 dB, respectively.
3-5 GHz CMOS功率放大器在130纳米CMOS超宽带应用
本文完成了一种工作在3ghz至5ghz频率范围内的宽带CMOS功率放大器(PA),用于130 nm CMOS工艺的超宽带(UWB)实现。所实现的功率放大器采用级联码方案(共源晶体管后接共门晶体管)。为了提高功率增益,采用两级级联码放大器,采用共源(CS)方案作为第三级,覆盖工作频带。该放大器的功率增益约为18.86 dB,平坦度约为±0.3。输出P1dB约为−3dbm。实现了输入和输出的大范围阻抗匹配。输入回波损耗(S11)、输出回波损耗(S22)和反向隔离(S12)分别约为<-5 dB、<- 3 dB和<-100 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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