A rail-to-rail-input chopper instrumentation amplifier in 28nm CMOS

Abstract

This paper presents a chopper instrumentation amplifier designed in 28nm CMOS technology. The operational amplifier has a rail-to-rail folded cascode input stage, which ensures a constant gm over the available common-mode range. It is characterized by a Nested Miller compensation. All transistors operate in sub-threshold region; thus the opamp has been designed through a specific procedure for sub-threshold operation. The chopper technique is exploited to reduce the input referred offset and noise. The circuit operates with 0.9V supply voltage and exhibits a simulated 106dB DC gain and 329kHz GBW. Montecarlo simulations demonstrate an offset distribution with 2.2μV standard deviation. The input noise spectral density is equal to 27nV/√Hz, giving a noise efficiency factor of 8.