{"title":"Mechanism study of positive-bias stress stability for solution processed oxide semiconductor TFT","authors":"Haoxin Li, Guangwei Xu, Shibing Long","doi":"10.1109/IFETC53656.2022.9948525","DOIUrl":null,"url":null,"abstract":"In this study, we investigated the positive bias stress (PBS) stability of solution-processed oxide semiconductor thin-film transistors (TFTs) under different stress gate voltages and temperatures. The ΔVon vs. stress time data were fitted very well by the stretched-exponential model. We also analyzed the data using a thermalization energy analysis method and found estimated barrier heights that agree with the stretched-exponential model fitting. We attributed the PBS instability to the deep interface traps at the interface between channel and gate insulator.","PeriodicalId":289035,"journal":{"name":"2022 IEEE International Flexible Electronics Technology Conference (IFETC)","volume":"30 5","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Flexible Electronics Technology Conference (IFETC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IFETC53656.2022.9948525","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this study, we investigated the positive bias stress (PBS) stability of solution-processed oxide semiconductor thin-film transistors (TFTs) under different stress gate voltages and temperatures. The ΔVon vs. stress time data were fitted very well by the stretched-exponential model. We also analyzed the data using a thermalization energy analysis method and found estimated barrier heights that agree with the stretched-exponential model fitting. We attributed the PBS instability to the deep interface traps at the interface between channel and gate insulator.