Design of a VLSI neural network arrhythmia classifier

Abstract

Artificial neural networks are now attractive tools to enhance and improve the efficiency, the capability and the features of instrumentation in applications related to measurements, system identification, and control. The aim of this paper is to implement an implantable cardiverter defibrillator (ICD) using an analog neural network. The paper describes a VLSI neural network chip to be implemented using 1.2 /spl mu/m CMOS technology, which acts as an intracardiac tachycardia classification system. A robust neural network is less sensitive to noise, drift and offsets inherent in analog applications. The proposed classifier uses two types of neural networks a Kohonen self organizing map (KSOM) circuit and a winner take all (WTA) circuit.