Transactional Test Environment for Faster and Early Verification of Digital Designs

Abstract

while verifying any digital design, it is very important to think about a feature or an issue in that design at the appropriate level of abstraction for getting better verification productivity. This is done by creating the environment to be capable enough to verify the design at all these abstraction levels. Although the interfaces of Design under Test (DUT) ultimately are represented by pin level activity, it is important and useful to maintain most of the verification tasks, like the stimuli generation and data collection, at the transaction level. This work concentrates on creation of a transaction level verification environment similar to the Universal Verification Methodology (UVM), which provides a set of communication channels to connect the components at transaction level using Transaction level Modelling (TLM) interfaces. The methodology described in this work provides a novel way for partitioning the environment and reducing the maintenance of low-level code through auto generation of synthesizable collectors and drivers as well as the first level code for the Bus Functional Models (BFM) and monitors in the test environment. These low-level components are developed to be robust enough to accept the stimuli from a variety of sources to the same agents and keeping the environment mostly independent of the mode of use. The simulation dump for transactions is stored and used as a stimuli to the same agents used during the simulation in the absence of DUT, this replay mode reduces the turnaround time for building the verification collaterals significantly. A case study on verifying a processor sleep handling logic like the sleep walking logics for Memory controller units being implemented these days, is done in this described environment to observe significant improvement in simulation time and verification collateral development.