Iterative methods for logarithmic subtraction

Abstract

The logarithmic number system (LNS) offers much better performance (in terms of power, speed and area) than floating point for multiplication, division, powers and roots. Moderate-precision addition (of like signs) in LNS generally can be done with table lookup followed by interpolation, whose implementation can be as, or more, efficient than the equivalent precision floating-point adder. The problem with LNS is the size of the table needed for subtraction. We consider iterative methods for logarithmic subtraction. The basis for the novel methods proposed here is that the subtraction logarithm is the inverse of the addition logarithm. Although the mathematics for this kind of logarithmic subtraction were first described during the time of Gauss, no modern designer has implemented an algorithm, like the one proposed here, which performs a binary search followed by an inverse interpolation. Additionally, we propose a novel initialization step for the binary search, which doubles the speed of the algorithm compared to a name, implementation. Combining the proposed method with other iterative methods may reduce the average execution time further. Synthesis results indicate the proposed methods are feasible for FPGA implementation.