An analog baseband chain for DS-UWB system

T. Koivisto, J. Maunu, E. Tiiliharju
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Abstract

In this paper, we propose a mixed-mode baseband chain using a high-speed analog Viterbi decoder. The circuit system architecture is presented with a link budget calculations and the baseband circuitry is introduced. Our target performance is 125 Mbit/s and 1 GbWs throughput at the distances of 10 and 1 m using a 1 GHz bandwidth dedicated to UWB systems between 3.1-4.9 GHz utilizing the analog Viterbi decoder. Proposed analog receiver architecture makes possible high-speed communication with decreased power consumption.
一种用于DS-UWB系统的模拟基带链
在本文中,我们提出了一种使用高速模拟维特比解码器的混合模式基带链。给出了电路系统的结构,进行了链路预算计算,并介绍了基带电路。我们的目标性能是125 Mbit/s和1 GbWs的吞吐量,距离为10米和1米,使用1 GHz带宽专用于3.1-4.9 GHz之间的UWB系统,利用模拟维特比解码器。所提出的模拟接收器架构使高速通信与低功耗成为可能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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