Impact of ground line position on CMOS interconnect behavior

Abstract

We investigate the impact of ground line position as well as the effects of conductive substrates with different conductivities of 10 S/m (low), 100 S/m (medium) and 10.000 S/m (high) on on-chip interconnects. Characteristic line parameters obtained from field calculations are validated with two-port network analyzer measurements of specially designed test structures in a frequency range up to 50 GHz.