CODESL: A Framework for System-Level Modelling, Co-simulation and Design-Space Exploration of Embedded Systems Based on System-on-Chip

Abstract

This paper presents CODESL, a SystemC-based hardware-software co-design and co-simulation framework for embedded systems based on System-on-Chip (SoC). This modelling platform, which works at Electronic System Level (ESL), enables early system functionality verification, as well as algorithm exploration before the final implementation prototype is available. It can validate the behaviour for both the hardware and the software modules of the embedded SoC, as well as the interaction between them with timed/cycleaccuracy. In addition, the platform also facilitates architecture exploration that assists the system designer in finding the best hardware-software partitioning. Results show that the proposed platform is capable of estimating the system execution cycle count within 5% deviation compared to the RTL deployment model for complex SoC embedded systems.