Benefit on interconnect performance of a relaxed wire density in a 45 nm node of the Back End of Line

Abstract

High speed digital ICs require short delay between successive gates and minimum crosstalk levels between adjacent interconnects. But crosstalk and delay performance are degraded with interconnect length. So designers can use large drivers with fast response to compensate global falloff due to long interconnects with critical delay and crosstalk levels. They must also trade off IC's cost and consumption against performance. The present study proposes to relax interconnect density requirement in some dedicated intermediate metal level of the Back End Of Line (BEOL). By doing this, delay and crosstalk level due interconnect itself are consequently reduced whatever the driver size. This solution is especially beneficial to long interconnect alleviating IC's design constraints.