PCB Channel Optimization Techniques for High-Speed Differential Interconnects

Abstract

Signal integrity (SI) performance is very much dependent on the cleanliness of a channel design in terms of impedance matching, insertion loss, reflection noise and signaling return path. This paper summarizes the layout optimization study done on USB3.2 Gen2 (10Gbps) signaling, which includes our proposal on via stub design, connector routing entry layer, placement of ground via stitching as well as component pad voiding size. Significant improvement in signaling eye margin is observed with the proposed channel optimization techniques. With the improved channel design, USB3.2 Gen2 is expected to be able to support longer routing length from the chip to its connector without the needs of adding a repeater. This will in turn provides cost saving to a computing platform design.