Testing logic circuits at different abstraction levels: An experimental evaluation

Abstract

The paper presents an experimental evaluation of test generation methods for digital circuits. Two methods are considered: an EFSM-based one, aimed at the code coverage of high-level (RTL) descriptions, and an equivalence-checking based on low-level (gate) description. High-level code and low-level fault coverage are measured for generated tests. Low-level mutants were generated for several fault models. Experiments have been performed for a subset of ITC'99 benchmarks. The results show that in most cases, the mutant coverage remains rather low for RTL tests. Vice versa, low-level tests have lower or the same RTL code coverage as high-level ones.