Enhanced Wallace Tree Multiplier via a Prefix Adder

U. Kumar, A. Fam
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引用次数: 4

Abstract

At the end of all fixed point multiplications is one last long addition that needs to be performed. In this paper, we show how the choice of this last adder has significant effect on the delay of the multiplier, in terms of time complexity. It is shown here that using a prefix adder for the final addition, causes the multiplication delay to increase as $\mathrm{O}({log}[N])$, as compared to the $\mathrm{O}(N)$ delay if a ripple carry adder is used instead. Simulations using spectre by Cadence, for 8,16,32, and 64 bit Wallace tree based multipliers, show that using a prefix adder instead of a ripple carry adder reduces the multiplier’s latency by up to 66% at the cost of minimal increase in power consumption.
通过前缀加法器增强华莱士树乘数
在所有定点乘法的末尾,需要执行最后一个长加法。在本文中,我们展示了最后一个加法器的选择如何在时间复杂度方面对乘法器的延迟产生重大影响。这里显示,使用前缀加法器进行最后的加法,会导致乘法延迟增加为$\mathrm{O}({log}[N])$,而如果使用ripple进位加法器则会导致乘法延迟增加为$\mathrm{O}(N)$。Cadence使用spectre对8位、16位、32位和64位基于Wallace树的乘法器进行了仿真,结果表明,使用前缀加法器而不是纹波进位加法器可将乘法器的延迟降低66%,而功耗增加最少。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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