Design of Low Phase-Noise LC- VCO at 2.5GHz by Body-Bias Technique Using CMOS 180 nm Technology

Abstract

Present work exhibits design of a Complementary MOS LC-VCO (Voltage Controlled Oscillator) along through body-biasing technique at 2.5 GHz. Body-biased technique has been introduced for reduction of power consumption and to obtain low Phase Noise (PN). Accordingly, body biasing technique leads to the lessening of supply voltage. An additional NMOS cross- coupled pairs in the traditional circuit of LC VCO have been incorporated to acquire better stability in oscillation frequency and to suppress the 1/f Noise. The projected VCO circuit has been implemented here with Cadence via Generic PDK 180nm technology. The simulation outcomes exhibit Phase Noise of −130.84 dBc/Hz at 1 MHz for 2.5 GHz working frequency. Observed power consumption of the proposed structure is 6.12 mW and Figure of Merit (FOM) is −236.14 dBc/Hz.