Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC

Abstract

In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave-pipelining achieves high speed without the above limitations. Wave-pipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks. This results in lower power at the cost of speed. Hybrid scheme is aimed at combining the advantages of both pipelining and wave-pipelining. Hence, we proposed the design and implementation of hybrid wavepipelined 2D-DWT using lifting scheme in this paper. For the purpose of comparison, non pipelined scheme as well as the scheme with pipelining within the blocks and between the blocks is implemented. From the results, it is concluded that the hybrid WP is faster than non-pipelined and requires less area, less clock routing complexity and lower power than pipelined.