Performance parameters optimization and implementation of adder/subtractor circuit using reversible logic approach

Abstract

Arithmetic digital processing sub-systems are considered as one of the major component of any electronic computing system. The adder/subtractor circuit is one of the vital part of computing systems such as arithmetic logic unit of any computer. Moreover, urge of efficient low loss processing devices are the basic need of the time. This need is the basic motivation for researchers to progress in the field of reversible circuit design approach. Low power VLSI circuits, DNA computing, optical computing, signal processing, quantum computing and nanotechnology etc. are some of the progressive fields with the application of the reversible logic concepts. In this paper, we have proposed an approach to design n-bit adder/subtractor circuits with available reversible logic gates only. The proposed design is compared with existing designs based on some selected factors such as total number of reversible gates used in the design, garbage outputs generated and quantum cost of the design. Based on the proposed design approach, 8-bit adder-subtractor circuit using reversible approach is simulated and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency. Application of this optimized circuit may be visualized for the designing of low power processing devices.