A 73μW 400Mbps stress tolerant 1.8V-3.6V driver in 40nm CMOS

Abstract

Architecture for I/O driver is proposed for high voltage (up to 3.6V) application by using low voltage devices. The proposed I/O is configurable to support multi supply range (1.8V-2.7V-3.6V). The buffer is designed in 40nm CMOS process by using standard 32Å oxide devices. This technique generates a set of dynamic bias signals as a function of input data sequence and the present value of the output which are fed to the cascoded stages to derive the next state of the output PAD. The experimental results confirmed successful operation up to 200 MHz with 10pF load on IO pad, with multiple supply rails.