FPGA implementation of modified serial montgomery modular multiplication for 2048-bit RSA cryptosystems

Abstract

RSA (Rivest, Shamir, Adleman) is one of the most widely used cryptographic algorithms worldwide to perform data encryption and decryption. An essential step in RSA computation lies on its modular multiplication which is relatively expensive and time consuming to be implemented in hardware. This paper proposes two modular multiplication architectures based on modified serial montgomery algorithm for 2048-bit RSA. By limiting the integer modulo that has sequence of A094358, a very simple and fast modular multiplication hardware can be developed. The first archictecture which incorporates 2048-bit adders performes better in term of latency (19010 Logic Cells, 2048 clock cycles or 0.0022 s), while the second architecture utilizing multiple smaller 128-bit adders offers less area consumption (8926 Logic Cells, 36864 clock cycles or 0.0031 s). An area multiplied with squared latency (AT2) can be used as trade-off parameter for choosing the most suitable design for certain need. For prototyping purpose, we have successfully synthesized and implemented our proposed designs written in VHDL using Altera Quartus II with Cyclone II EP2C70F896C6 FPGA as a target board.