G. Amendola, Y. Blanchard, A. Exertier, S. Spirkovitch, G. Lu, G. Alquié
{"title":"A CMOS, self-biased charge amplifier","authors":"G. Amendola, Y. Blanchard, A. Exertier, S. Spirkovitch, G. Lu, G. Alquié","doi":"10.1109/MMICA.1999.833580","DOIUrl":null,"url":null,"abstract":"In this article a charge amplifier dedicated to the signal processing of a capacitive silicon microphone is described. One feature of this amplifier is the implementation of a self-biased technique. It is a transconductance amplifier having a very high output resistance. The current consumption is quite low (20 /spl mu/A without the bias circuit) and the dimensions are 210 /spl mu/m by 170 /spl mu/m (including all capacitors). The amplifier has been designed and fabricated in 0.8 /spl mu/m CMOS technology. Both simulation and measurement results have shown the analog memorization of DC bias voltage.","PeriodicalId":221297,"journal":{"name":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMICA.1999.833580","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this article a charge amplifier dedicated to the signal processing of a capacitive silicon microphone is described. One feature of this amplifier is the implementation of a self-biased technique. It is a transconductance amplifier having a very high output resistance. The current consumption is quite low (20 /spl mu/A without the bias circuit) and the dimensions are 210 /spl mu/m by 170 /spl mu/m (including all capacitors). The amplifier has been designed and fabricated in 0.8 /spl mu/m CMOS technology. Both simulation and measurement results have shown the analog memorization of DC bias voltage.