{"title":"HDMI video scaling on an all-programmable SoC","authors":"Chih-Yao Tsai, Chaoxiu Chen","doi":"10.1109/ICCPS.2016.7751118","DOIUrl":null,"url":null,"abstract":"We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.","PeriodicalId":348961,"journal":{"name":"2016 International Conference On Communication Problem-Solving (ICCP)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference On Communication Problem-Solving (ICCP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCPS.2016.7751118","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
We propose a High-Definition Multimedia Interface (HDMI) video scaling system based on an all-programmable SoC, which can be used in any image processing system requiring a two-dimensional (2D) interpolation accelerator. This structure work on a platform-based SoC environment. By the AXI Video Direct Memory Access (AXI VDMA), video data are directly transferred between DDR3 memory and the built-in FPGA where the proposed buffering scheme and interpolation accelerator are implemented. We store video data in the DDR3 memory and the interpolation accelerator performs real-time video scaling. An experiment with HDMI video input from a Microsoft Windows PC and HDMI video output to another display proves the effectiveness of the real-time video scaling.