{"title":"A reconfigurable computing architecture using magnetic tunneling junction memories","authors":"Victor Silva, J. Fernandes, M. Véstias, H. Neto","doi":"10.1109/FPL.2013.6645616","DOIUrl":null,"url":null,"abstract":"This work presents a new dynamically reconfigurable architecture that uses magnetic tunneling junctions to implement non-volatile reconfiguration memories. The magnetic-based storage elements further provide a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional array of double precision floating-point run-time reconfigurable execution units. The configuration information defines the operation to be executed and the data flow intra and inter execution units. A prototype design of the coarse-grained reconfigurable array has been implemented targeting a 65nm CMOS technology. The obtained results confirm that the proposed architecture provides a significant computational density and that the magnetic memories provide a very area efficient multi-context based run-time reconfigurability.","PeriodicalId":200435,"journal":{"name":"2013 23rd International Conference on Field programmable Logic and Applications","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 23rd International Conference on Field programmable Logic and Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPL.2013.6645616","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This work presents a new dynamically reconfigurable architecture that uses magnetic tunneling junctions to implement non-volatile reconfiguration memories. The magnetic-based storage elements further provide a very effective implementation of multi-context planes. The proposed architecture is organized as a 2-dimensional array of double precision floating-point run-time reconfigurable execution units. The configuration information defines the operation to be executed and the data flow intra and inter execution units. A prototype design of the coarse-grained reconfigurable array has been implemented targeting a 65nm CMOS technology. The obtained results confirm that the proposed architecture provides a significant computational density and that the magnetic memories provide a very area efficient multi-context based run-time reconfigurability.