A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS

Abstract

The adaptive clock circuit provides the deferred reference clocks for the adaptive voltage-frequency scaling (AVFS) system. However, coping with the high-precision demands of reference clocks remains a challenge. To address these issues, this paper presents an adaptive clock circuit for the AVFS system consisting of a time-to-digital converter, a configurable delay chain, and a code-to-code converter. We implement 3 technologies to improve performance: 1) a multi-level configurable delay chain (CDC) is adopted to obtain a wide range of operating frequencies; 2) the source/drain capacitance of an NMOS transistor operates as a unit load capacitance to achieve ultra-fine delay adjustment; 3) one-hot transmission gate multiplexers are adopted to reduce the propagation latency deviation from multiplexers' input ports to the output's. Verified in 28nm process, simulation results show that the proposed circuit achieves a precision of 0.172ps at TT0.9V25°C, which reduces the impact of PVT variations.