Automated generation of core test description file for hierarchical test

Abstract

Most of modern system-on-chip (SoC) contain multiple hierarchy levels. This imposes specific requirements on the test solution, test access mechanism (TAM), and porting of core test patterns. Another challenge for multi-core hierarchical SoCs is the test integration time and automated generation of hierarchical test network and TAM. This paper presents a method for automated generation of core test description. The core test description file transfers the core test information required for automated generation of hierarchical test system. The test description file can contain bulky core-specific information on core test features necessary for hierarchical test. Automated generation of core test description allows drastically reduce hierarchical system generation and integration time.