A 5.8-μ W 61.29-dB-SNDR 10-bits Configurable EEG Acquisition System

L. Pham-Nguyen, Viet Nguyen-Thien, Tien-Dung Le Van, Khai Quang Nguyen, Huy-Dung Han
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引用次数: 0

Abstract

In this paper, a fully-integrated acquisition system consists of a configurable analog front-end (AFE) and an ultra-low-power 10-bit Successive Approximation Register (SAR) ADC is designed to capture and digitize the electroencephalogram (EEG) signal. The AFE exhibits a DC gain ranging from 60 dB to 84.7 dB, a bandwidth of 0.5 Hz to 100 Hz, 0.82-μVrms input-referred noise, and 5.8-μW power consumption. The ADC shows a peak SNR and SNDR of 61.31 dB and 61.29 dB, respectively, at a 77.7-dB spurious-free dynamic range (SFDR), while consuming only 16.3 nW. This system is designed in a 180-nm CMOS process with a voltage supply of 1.2 V.
5.8 μ W 61.29 db - sndr 10位可配置脑电信号采集系统
本文设计了一个完全集成的采集系统,该系统由一个可配置的模拟前端(AFE)和一个超低功耗的10位逐次逼近寄存器(SAR) ADC组成,用于捕获和数字化脑电图(EEG)信号。直流增益范围为60db ~ 84.7 dB,带宽范围为0.5 Hz ~ 100hz,输入参考噪声为0.82 μ vrms,功耗为5.8 μ w。在77.7 dB无杂散动态范围(SFDR)下,ADC的峰值信噪比和信噪比分别为61.31 dB和61.29 dB,而功耗仅为16.3 nW。该系统采用180nm CMOS工艺设计,电源电压为1.2 V。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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