L. Pham-Nguyen, Viet Nguyen-Thien, Tien-Dung Le Van, Khai Quang Nguyen, Huy-Dung Han
{"title":"A 5.8-μ W 61.29-dB-SNDR 10-bits Configurable EEG Acquisition System","authors":"L. Pham-Nguyen, Viet Nguyen-Thien, Tien-Dung Le Van, Khai Quang Nguyen, Huy-Dung Han","doi":"10.1109/ICCE55644.2022.9852040","DOIUrl":null,"url":null,"abstract":"In this paper, a fully-integrated acquisition system consists of a configurable analog front-end (AFE) and an ultra-low-power 10-bit Successive Approximation Register (SAR) ADC is designed to capture and digitize the electroencephalogram (EEG) signal. The AFE exhibits a DC gain ranging from 60 dB to 84.7 dB, a bandwidth of 0.5 Hz to 100 Hz, 0.82-μVrms input-referred noise, and 5.8-μW power consumption. The ADC shows a peak SNR and SNDR of 61.31 dB and 61.29 dB, respectively, at a 77.7-dB spurious-free dynamic range (SFDR), while consuming only 16.3 nW. This system is designed in a 180-nm CMOS process with a voltage supply of 1.2 V.","PeriodicalId":388547,"journal":{"name":"2022 IEEE Ninth International Conference on Communications and Electronics (ICCE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Ninth International Conference on Communications and Electronics (ICCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE55644.2022.9852040","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, a fully-integrated acquisition system consists of a configurable analog front-end (AFE) and an ultra-low-power 10-bit Successive Approximation Register (SAR) ADC is designed to capture and digitize the electroencephalogram (EEG) signal. The AFE exhibits a DC gain ranging from 60 dB to 84.7 dB, a bandwidth of 0.5 Hz to 100 Hz, 0.82-μVrms input-referred noise, and 5.8-μW power consumption. The ADC shows a peak SNR and SNDR of 61.31 dB and 61.29 dB, respectively, at a 77.7-dB spurious-free dynamic range (SFDR), while consuming only 16.3 nW. This system is designed in a 180-nm CMOS process with a voltage supply of 1.2 V.