K. Miyaji, S. Noda, T. Hatanaka, Mitsue Takahashi, S. Sakai, K. Takeuchi
{"title":"A 1.0V power supply, 9.5GByte/sec write speed, Single-Cell Self-Boost program scheme for Ferroelectric NAND Flash SSD","authors":"K. Miyaji, S. Noda, T. Hatanaka, Mitsue Takahashi, S. Sakai, K. Takeuchi","doi":"10.1109/IMW.2010.5488322","DOIUrl":null,"url":null,"abstract":"A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe-) NAND flash memories. In the proposed SCSB scheme, only the channel voltage of the cell to which the program voltage VPGM is applied is self-boosted in the program-inhibit NAND string. The proposed program scheme shows an excellent tolerance to the program disturb at the power supply voltage, VCC=1.0V. The power consumption of the Fe-NAND at VCC=1.0V decreases by 86% compared with the conventional floating gate (FG-) NAND at VCC=1.8V without degrading the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.9 times. As a result, the 9.5GByte/sec write throughput of the Fe-NAND SSD is achieved for an enterprise application.","PeriodicalId":149628,"journal":{"name":"2010 IEEE International Memory Workshop","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2010.5488322","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0V power supply operation in Ferroelectric (Fe-) NAND flash memories. In the proposed SCSB scheme, only the channel voltage of the cell to which the program voltage VPGM is applied is self-boosted in the program-inhibit NAND string. The proposed program scheme shows an excellent tolerance to the program disturb at the power supply voltage, VCC=1.0V. The power consumption of the Fe-NAND at VCC=1.0V decreases by 86% compared with the conventional floating gate (FG-) NAND at VCC=1.8V without degrading the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.9 times. As a result, the 9.5GByte/sec write throughput of the Fe-NAND SSD is achieved for an enterprise application.