Fast Congestion Aware Routing for Pin Assignment

Abstract

Macroblock (aka partition) pin assignment and routing are important tasks in typical top-down hierarchical physical design. Routers use pin locations as connection points to route the design with a goal of minimizing congestion. However, determining suitable pin locations it self depends on availability of congestion free routing topology as a seed input. This results in a catch-22 situation. In this paper, we present an approach, during prototyping phase, to generate fast-and- dirty congestion free routing topology, in top channels. This is real chip routing topology, in the sense that, the routing topology of every net adheres to physical hierarchy, as would happen during hierarchical implementation. This is passed as seed to pin assignment engine, which thus, results in congestion-free pin locations. The novelty of this approach lies in efficient detection of those inter-partition nets whose routing topology have little or no bearing to top channel congestion. These nets are then either not routed or routed in a fast hierarchy unaware manner. We will show that this routing topology is good enough (less than 10% error margin) to establish suitable cross points at partition boundaries, while the speed up achieved is around 6X compared to routing all nets in hierarchy aware manner. Experimental results demonstrate its efficiency and effectiveness. Furthermore, it can also be effectively used as seed input for decisions like channel sizing between partitions, and budgeting timing constraints to partitions.